I am in no way responsible for ReSlow. The article below is a partial translation of an article written by Pekka Pessi in the late Finnish Commodore-magazine. Praise him if you get it to work. Start looking from http://www.hut.fi/~ppessi. Don't know if it's him, though :)
In the beginning of the article Pessi talks about installing a
newer Agnus (8372A) to your amiga and putting 512kb memory on the
mobo. You can get that info someplace else. Or I can write it if
you insist. So, on to the ReSlow device:
How it works.
Click for schematics. In the schematics, the area inside the dotted line is the ReSlow device. Below that are the changes to the motherboard - the three wores that should be cut.
ReSlow works with A500 revision 6, but the instructions can be utilised with older A500's and B2000's (Amiga 2k w/ mono video output connector). The schematics of the board (found in the manual) are most useful in seeking out the signals used.
The device is very simple. It has 3 chips that choose which 512kB memory bank is to be used. The RAS-signal of the chosen bank (pin 4 in the memory circuits) is put to 0.
ReSlow alters the RAS-signals between Agnus and the memory banks, decoding RAS0 and RAS1 into 3 different signals depending on A23 and /DBR. RAC0 and RAC1 choose the chip-RAM banks, RAF0 chooses the slow-RAM bank. It is used only when /DBR and A23 are 1. The only problem with the device is refresh. Memory refresh also happens during the DMA, when both RAS signals from Agnus are 0. Two NOR-gates ensure that also slow-RAM is refreshed.
The problem with ReSlow is timing. I used ALS-type chips, but they might not work in all machines. F- or AS-type chips should then be used.
Making it work.
An image of an installed ReSlow. (Wiring differs from the schematics, but is identical in functioning.)
The chips should be put into sockets, if and when additional speed is required. The power for the device is received by wiring it into some TTL-chip on the motherboard (e.g. U11, 74LS373), to pins 20 (+5V) and 10 (earth).
A23 is most easily received from JP2. The /DBR wire might be wise to be soldered to the throughpull below Gary, found most easily by following the strip from Gary's pin 15. RAS0 and RAS1 are found on pins 15 and 2 (respectively?) of U35 (74F244).
Both connections on JP3 are opened, and the RC0 signal from ReSlow is soldered into the upper-left square in JP3, RC2 to the lower-right corner. RAS1-signal from U38 pin 18 must be cut before the memory-add-on connector. The RC1 wire is then soldered to the strip going to the memory-add-on connector.
Does it work?
J7A must be in its original position, because it tells Gary the machine has slow-RAM. Then the computer can be powered on. If there is not a full megabyte of chip, something is wrong with the timings. Once the additional memory is installed to the mobo, the computer should be tested before building ReSlow. Signal RC0 stands for $000000-$07FFFF, RC1 for $080000-$0FFFFF, and RC2 for $C00000-$C7FFFF.
An oscilloscope is a good help in debugging, it can be used to check all signals RC0-RC2 get negative pulses.